1. Field of the Invention
This disclosure relates to a semiconductor device, and more particularly, to a field effect transistor having a gate all around (GAA) structure and a method of manufacturing the same.
2. Description of the Related Art
A recent rapid development in the information and communication fields, and a popularization of information media, such as computers, have brought rapid progress of semiconductor devices. A high-integration of semiconductor devices has brought about research for several kinds of methods to reduce a feature size of individual devices formed on a substrate from a functional viewpoint, and to increase performance of the devices. In such methods a field effect transistor (FET) is utilized to improve an integration of the device on the basis of a silicon semiconductor technique and a CMOS (Complementary Metal Oxide Semiconductor) technique. A scaling-down of a general planar field effect transistor in conformity with the high-integration of the devices lowers performance or reliability of the devices, thus three-dimensional structures such as a vertical transistor have been proposed instead of a planar type structure. As an example, a fin field effect transistor (FET) has been proposed in the field. The fin shape generally is like a dorsal of a fish, which is a vertical structure of a body of the transistor.
In detail, in an FET of a planar structure that employs the existing single-crystal silicon substrate as a channel, a length of a gate electrode is scaled down under 500 Å, thus being very sensitive to a process condition and difficult to control characteristics of devices in a manufacturing process. Moreover, when a length of channel is about 300 Å, the performance of the devices may suffer. For example, in a field effect transistor (FET) developed by Intel Corp., a length of gate electrode is about 300 Å, and, a current-to-voltage (I-V) characteristic is not prominent as compared with a conventional FET having a channel of over about 500 Å. An area occupied by one FET is not reduced as compared with a conventional case because of a spacer region formed on sidewalls of a non-scaled down gate electrode. Thus integration is not improved. Therefore, methods of forming the three-dimensional FET device are, for example, DELTA (fully Depleted Lean-channel Transistor) and a GAA (Gate All Around) structure. An example of MOSFET (Metal Oxide Semiconductor Field Effect Transistor) having the DELTA structure is disclosed in U.S. Pat. No. 4,996,574. The DELTA structure has an active layer where a channel will be formed. The active layer has a predetermined width and protrude vertically. In this structure, also a gate electrode is formed to surround the vertically protruded channel portion. Thus, a height of the protruded portion becomes a width of the channel and a width of the protruded portion becomes a length of a gate region where the channel is formed. In such an FET having the DELTA structure, an entire face of the protruded portion can be all used as the channel, thus the width of the channel has a remarkably increased effect as compared with an FET of the planar structure. That is, the FET of the DELTA structure can prevent a narrow channel effect based on a reduction of channel width because a length of the channel is not reduced by a reduction of the device formation region as compared with a general transistor. If a width of the protruded portion is reduced, a depletion layer of the channel formed in the gate region may be depleted fully or partially, thus increasing a conduction of the channel. In the meantime, if a semiconductor device of the DELTA structure is applied to a general silicon substrate, the silicon substrate is processed in such a way that a portion where a channel is formed on the silicon substrate, is protruded. Then, the protruded portion is covered with an oxide prevention layer and the resulting structure is oxidized. If the oxidization is performed excessively, the protruded portion having a channel formation and a portion connected to a substrate body are oxidized by oxygen atoms diffused to a side direction from a portion not protected by the oxide prevention layer. Thus, the channel is separated from a main body portion of the silicon substrate. In these procedures a thickness of the channel of the connection part becomes small while the channel separation is performed by the excessive oxidization, and a single-crystal layer is pressurized and damaged under the oxidation procedure. Furthermore, if an SOI (Silicon On Insulator) type silicon substrate, in which an interlayer dielectric layer is formed in a lower part of semiconductor substrate, is applied to the formation of the DELTA structure, an SOI layer is etched to become a smaller width and to form a channel portion. Thus a problem caused by the excessive oxidation in using the single-crystal silicon substrate is prevented. However, if an FET of a double-gate or tri-gate structure, similar to the DELTA structure manufactured on the single-crystal silicon substrate, is manufactured intact on the SOI type silicon substrate, and that its characteristic is analyzed, then a body of the transistor is not coupled with the substrate by a device characteristic of the SOI type silicon substrate. Thus a floating body effect can be caused, lowering the performance of the devices.
Meanwhile, in an FET of the GAA structure a gate electrode is formed, surrounding an entire face of active region of a bridge structure, thus in comparison with the FET of the DELTA structure, the FET of the GAA structure has more prominent electrical characteristics. An example of an FET having the GAA structure is disclosed in U.S. Pat. No. 6,495,403.
FIG. 1 is a perspective view illustrating a conventional structure of an FET.
A method of manufacturing the FET having the structure of FIG. 1 will be described as follows.
Referring to FIG. 1, on an active region 2 of a silicon substrate 1 selectively exposed by a dielectric layer 3 or an insulation layer, a single-crystal silicon germanium SiGe layer (not shown) or a Ge layer having a predetermined thickness is formed through a selective epitaxial growth method. Then, on the single-crystal silicon germanium layer or germanium layer, and the dielectric layer 3 or the insulation layer, a silicon layer is formed through a non-selective epitaxial growth method. Herewith, the silicon layer formed on the active region 2 where the SiGe or Ge was formed, is grown as a single-crystal silicon layer 5a, and the silicon layer formed on the dielectric layer 3 or the insulation layer is formed of a polysilicon layer 5b. On the single-crystal silicon layer 5a a channel impurity region may be formed by ion implanting a first conductive impurity in the single-crystal silicon layer 5a and the polysilicon layer 5b. 
The single-crystal silicon layer 5a and the polysilicon layer 5b are patterned through a general photolithography and etching method, to form a fin active region 5 of one direction. To form the fin active region 5 of a bridge shape, a silicon germanium layer or germanium layer is removed to form a tunnel 7. On the polysilicon layer 5b and the single-crystal silicon layer 5a of the bridge shape, a gate insulation layer 8 and 9 is formed, and then conductive material is formed, surrounding an overall face of the single-crystal silicon layer 5a on which the gate insulation layer 8 and 9 is formed. The conductive material is patterned through a general photolithography and etching method, to form a gate electrode 10. The gate electrode 10 is formed to have a distance smaller than or equal to the single-crystal silicon layer 5a. 
Last, a second impurity of a low density is ion implanted in the single-crystal silicon layer 5a and the polysilicon layer 5b exposed by the gate electrode 10, to form a first impurity region (not shown), and respective contacts 11, 12 and 13 are formed on the gate electrode 10 and source/drain regions.
In the method of manufacturing the FET according to the prior art, the selective epitaxial growth is used to form the single-crystal silicon layer 5a on the silicon germanium layer or germanium layer and to form the gate electrode 10 surrounding an entire face of the single-crystal silicon layer 5a. Accordingly, a single-crystal silicon layer having an electrical characteristic more prominent than the polysilicon layer 5b grown through the existing epitaxial growth method can be used as a channel formation region.
However, a method of manufacturing an FET according to the prior art has the following problems.
First, the single-crystal silicon layer 5a used as a channel formation region is grown by an epitaxial growth method that may have a crystalline defect because of a generation rate that is higher than a bulk silicon substrate. Thus a reliability of these devices may be lowered.
Second, conductive material formed in a lower part of the tunnel 7 having a bridge structure is not reproducibly removed when the conductive material is removed by a photolithography and etching method using a general dry or wet etching (in forming the gate electrode 10 surrounding the single-crystal silicon layer 5a of the bridge structure). Thus, a length of channel cannot be controlled precisely.
Third, an active region of the source/drain region is formed of polysilicon having a low electrical conductivity as compared with the single-crystal silicon.